1. Field of the Invention
The present invention relates to a characteristic extraction technique, a characteristic evaluation technique, a recording medium and a semiconductor device.
2. Description of the Background Art
In the process of developing a logic device, circuit simulation is widely employed for estimating the optimum margins on circuit characteristics. FIG. 31 is an explanatory diagram showing the outline of circuit simulation. A device referred to as a circuit simulator is employed for executing the circuit simulation. Data related to the characteristics of each element forming the circuit (device) to be simulated and data (referred to as xe2x80x9ccircuit connection informationxe2x80x9d) related to connection conditions for each element are input in the circuit simulator. The circuit simulator executes simulation on the basis of the input data, and outputs data related to the characteristics of the circuit. On the basis of the output data, an operator can determine whether or not the circuit operates with the optimum margins and feed back the results of the determination to development of the device.
In development of the state-of-the-art logic device, circuit simulation based on the well-known SPICE model forming the world standard is generally employed in particular. Further, modeling not only employing typical values as the characteristics of the element but also adopting dispersion of the characteristics of the element from the best to the worst values in consideration of errors (process errors) occurring in the process of manufacturing the device, i.e., worst/best modeling is performed. In the worst/best modeling employing SPICE, a method based on E-T (electrical test) data forms the main stream.
In this method, a group of parameters referred to as E-T data are input as the data related to the characteristics of the element. Circuit simulation is executed after the input E-T data are converted to a group of parameters referred to as SPICE parameters necessary for executing simulation based on the SPICE model. The E-T data, which are parameters associable with the SPICE parameters and having physical meanings, can advantageously be directly extracted from the electric characteristics of the element in a short time.
If the element is a MOSFET (MOS field-effect transistor), a threshold voltage Vth, channel shortening DL, external resistance Rds, channel narrowing DW, mobility xcexc and a saturation velocity Vsat (or a parameter expressing a velocity saturation effect in place of Vsat) are extracted as the E-T data. FIG. 32 is a sectional view of a MOSFET for illustrating the physical meanings of these parameters. The channel shortening DL is defined as the difference between a channel length (mask length) Lm as the dimension of a mask and an electrically effective channel length (effective channel length) Leff. That is,
DL=Lmxe2x88x92Leffxe2x80x83xe2x80x83(e1)
While not shown in FIG. 32, the channel narrowing DW is similarly defined as the difference between a channel width (mask width) Wm as the dimension of the mask and an electrically effective channel width (effective channel width) Weff. That is,
DW=Wmxe2x88x92Weffxe2x80x83xe2x80x83(e2)
Total resistance between a source electrode SS and a drain electrode DD is given by the sum of resistance (channel resistance) Rch of a channel region Ch and the external resistance Rds. Both of the source electrode SS and the drain electrode DD include electrode wires. The external resistance Rds is a resistance component outside the channel region Ch, and generally includes resistance (source/drain resistance) of a source region S and a drain region D and resistance of the electrodes (including the electrode wires). Assuming that Rtot represents the total resistance,
Rtot=Rch+Rdsxe2x80x83xe2x80x83(e3)
The external resistance Rds is not important in an element having a large channel length due to large channel resistance Rch. In a refined element, however, the external resistance Rds is important due to small channel resistance Rch. In particular, resistance components of electrodes are unignorable. A gate insulator film OX having a thickness Tox is interposed between a gate electrode and a semiconductor layer.
However, a method of extracting these parameters related to the MOSFET in a mutually matching form has not been known in general. A highly precise extraction method has been devised as to the channel shortening DL and the external resistance Rds as described in Japanese Patent Application No. 10-213019 (1998) (hereinafter referred to as literature 1), for example, and a method of precisely extracting the channel narrowing DW has been devised as described in Japanese Patent Application No. 10-239148 (1998) (hereinafter referred to as literature 2), for example. In relation to the mobility xcexc and the saturation velocity Vsat, however, there is known no method of performing extraction in a form matching with the remaining parameters.
In relation to the mobility xcexc, for example, the Moneda method is generally known as a typical extraction method. The Moneda method is disclosed in F. H. De La Moneda, H. N. Kothcha and M. Shatzkes, xe2x80x9cMeasurement of MOSFET Constantsxe2x80x9d, IEEE Elect. Dev. Lett., EDL-3(1), pp. 10, 1982 (hereinafter referred to as literature 3). In the Moneda method, the following equation (1) is assumed as the model of the mobility xcexc:                     μ        =                  μ0                      1            +                          θ              ⁡                              (                                  Vgs                  -                  Vth                                )                                                                        (        1        )            
where Vgs represents a gate-to-source voltage, xcexc0 represents the mobility xcexc at the time when the gate-to-source voltage Vgs matches with the threshold voltage Vth, and xcex8 represents a parameter.
In this case, the total resistance Rtot is given by the following equation (2):                     Rtot        =                  Rds          +                      S            ⁡                          (                              θ                +                                  1                                      Vgs                    -                    Vth                    -                                          Vds                      /                      2                                                                                  )                                                          (        2        )            
where the parameter S is given by the following equation (3):                     S        =                              Lm            -            DL                                μ0            ·            Cox            ·            Weff                                              (        3        )            
where the parameter Cox is the capacitance of the gate insulator film OX.
On the basis of the equation (2), the mobility xcexc is extracted along the following procedure:
Step 1: Drain-source current Ids vs. gate-to-source voltage Vgs characteristics (Idsxe2x88x92Vgs characteristics) in a linear region of a plurality of transistors (MOSFETs) different only in channel length from each other are measured.
Step 2: An Rtotxe2x88x921/(Vgsxe2x88x92Vthxe2x88x92Vds/2) characteristic is plotted for each transistor as shown in FIG. 33, for performing linear fitting. Vds represents a drain-to-source voltage. In this case, slope of the straight line corresponds to S in the equation (3), and the vertical axis intercept is xcex8xc2x7S+Rds (=R).
Step 3: From the result in the step 1, an Sxe2x88x92Lm characteristic is plotted as shown in FIG. 34, for performing linear fitting. In this case, slope of the straight line is 1/(xcexc0xc2x7Coxxc2x7Weff) (=C).
Step 4: Assuming that Wm≈Weff and Cox=xcex5ox/Tox, xcexc0 is given by Tox/(Cxc2x7xcex5oxxc2x7Wm) from the result in the step 3, where xcex5ox represents a factor of proportionality between the capacitance Cox and 1/Tox. An actual value may be given to Cox.
Step 5: An Rxe2x88x92S characteristic is plotted as shown in FIG. 35 from the result in the step 1, for performing linear fitting. In this case, slope of the straight line is xcex8.
In the Moneda method, as hereinabove described, primary deterioration is assumed in relation to the mobility xcexc, for extracting the channel shortening DL, the external resistance Rds and the parameters xcexc0 and xcex8 related to the mobility xcexc at the time when the gate-to-source voltage Vgs is around the threshold voltage Vth. Hence, a secondary mobility deterioration factor or external resistance Rds having Vgs dependency cannot be extracted.
This also applies to a well-known extraction method related to the velocity saturation effect. In a conventional typical method extracting a parameter related to the saturation effect, the following equation (4) is employed:                               1          β0                =                              Leff            +                          U1              ·              Vds                                            μ0            ·            Cox            ·            Weff                                              (        4        )            
where U1 represents a velocity saturation coefficient.
On the basis of the equation (4), the velocity saturation effect is extracted along the following procedure:
Step 1: Idsxe2x88x92Vgs characteristics in a linear region of a plurality of transistors (MOSFETs) different only in channel length from each other are measured.
Step 2: For each transistor, xcex2 is regarded as (maximum value of slope of Idsxe2x88x92Vds characteristics)Vds.
Step 3: A 1/xcex20-Leff characteristic is plotted as shown in FIG. 36, for performing linear fitting. In this case, slope of the straight line is 1/(xcexcxc2x7Coxxc2x7Weff) (=A). The vertical axis intercept is U1xc2x7Vds/xcexc0xc2x7Coxxc2x7Weff (=B).
Step 4: The velocity saturation coefficient U1 is given by B/(Axc2x7Vds) from the result in the step 3.
However, it is said that this method is problematic in extraction precision since the velocity saturation coefficient U1 is not extracted in a form matching with the remaining E-T data but influenced by the external resistance Rds.
In the conventional extraction methods, as hereinabove described, the mobility xcexc and the velocity saturation effect are not extracted in a form matching with extraction of the parameters DL, Rds, DW etc., and hence deterioration of precision is disadvantageously unavoidable.
A characteristic extraction device according to a first aspect of the present invention, extracting a parameter expressing a velocity saturation effect of a MOS transistor, comprises (a) an effective channel length extraction part receiving a signal expressing measured data of a characteristic of the MOS transistor and extracting an effective channel length of the MOS transistor for at least two drain-to-source voltages on the basis of the signal, and (b) a parameter calculation part calculating the parameter on the basis of the extracted effective channel length and outputting a signal expressing its value.
In the device according to the first aspect, since the parameter expressing the velocity saturation effect is extracted on the basis of the effective channel length, the parameter is precisely extracted in a form matching with channel shortening and external resistance, which are other parameters forming E-T data.
According to a second aspect of the present invention, the parameter calculation part (b) includes (b-1) a U1 calculation part calculating a velocity saturation coefficient U1 as the parameter expressing the velocity saturation effect by regarding the effective channel length as a function Le(Vds) of the drain-to-source voltages Vds and assuming the following relation with another parameter Leff:
Le(Vds)=Leff+U1xc2x7Vds
According to the second aspect, the velocity saturation coefficient is precisely extracted as the parameter expressing the velocity saturation effect in a form matching with channel shortening and external resistance.
According to a third aspect of the present invention, at least two drain-to-source voltages are two drain-to-source voltages Vds1 and Vds2, and the U1 calculation part (b-1) includes (b-1-1) a device part expressing a set of values Le(Vds1) and Le(Vds2) of the function calculated by using the relation for the two drain-to-source voltages Vds1 and Vds2, as a data point on a graph for each of at least two MOS transistors, (b-1-2) a device part expressing a group of the data points in a straight line on the graph, and (b-1-3) a device part obtaining the velocity saturation coefficient U1 by dividing the value Le(Vds2) at the Le(Vds1) being about zero on the straight line by the difference Vds2xe2x88x92Vds1 between the value Vds1 and the value Vds2.
According to the third aspect, the velocity saturation coefficient, which is obtained on the basis of an intercept on a straight line expressing a set of values Leff(Vds1) and Leff (Vds2) of the function on a graph or an approximate value thereof, is readily and precisely provided.
According to a fourth aspect of the present invention, at least two drain-to-source voltages are two drain-to-source voltages Vds1 and Vds2, and the U1 calculation part (b-1) includes (b-1-1) a device part expressing a set of a ratio Le(Vds2)/Le(Vds1) and an inverse 1/Le(Vds1) obtained from values Le(Vds1) and Le(Vds2) of the function calculated by using the relation for the two drain-to-source voltages Vds1 and Vds2, as a data point on a graph for each of at least two MOS transistors, (b-1-2) a device part expressing a group of the data points in a straight line on the graph, and (b-1-3) a device part obtaining the velocity saturation coefficient U1 by dividing slope of the straight line by the difference Vds2xe2x88x92Vds1 between the value Vds1 and the value Vds2.
According to the fourth aspect, the velocity saturation coefficient, which is obtained on the basis of slope of the straight line expressing the set of Leff(Vds2)/Leff (Vds1) and I/Leff(Vds1) on the graph, is readily and precisely provided.
According to a fifth aspect of the present invention, the effective channel length extraction part (a) includes (a-1) a device part receiving signals expressing measured data of characteristics of at least two MOS transistors different only in channel length from each other as the signals expressing the measured data and obtaining data related to drain-to-source currents Ids vs. gate-to-source voltages Vgs under at least two drain-to-source voltages Vds as to at least two MOS transistors different only in the channel length from each other on the basis of the signals, (a-2) a device part expressing a set of total resistance defined as Vds/Ids and the channel length for each of at least two MOS transistors, each of at least two drain-to-source voltages Vds and each of at least two gate overdrives Vgt as data points on a graph, (a-3) a device part individually expressing each group of the data points having both of the drain-to-source voltage Vds and the gate overdrive Vgt in common in a straight line, and (a-4) a device part calculating the effective channel length for each of at least two drain-to-source voltages Vds from an intersection between the straight lines having different gate overdrives Vgt.
According to the fifth aspect, the effective channel length, which is calculated from the intersection between the straight lines expressing total resistance vs. channel length with different gate overdrives on the graph, is readily and precisely provided.
According to a sixth aspect of the present invention, the characteristic extraction device further comprises (c) an f extraction part receiving signals expressing measured data of characteristics of at least two MOS transistors different only in channel length from each other and extracting channel resistance f(Vgt) per unit effective channel length as a function of a gate overdrive Vgt on the basis of the signals, (d) a DW extraction part receiving signals of measured data of characteristics of at least two MOS transistors different only in channel width from each other and extracting channel narrowing DW(Vgt) as a function of the gate overdrive Vgt on the basis of the signals, (e) a xcexc calculation part deciding the parameter so as to fit mobility xcexc (Vgt) as a function of the gate overdrive Vgt expressed by the following relations employing a capacitance Cox of a gate insulator film, a drain-to-source voltage Vds and a channel width Wm:             1              μ        ⁡                  (          Vgt          )                      =                  h        ⁡                  (          Vgt          )                    ·      Cox      ·              (                  Vgt          -                      Vds            2                          )              and                    h        ⁡                  (          Vgt          )                    =                        f          ⁡                      (            Vgt            )                          ·                  (                      Wm            -                          DW              ⁡                              (                Vgt                )                                              )                      ,          xe2x80x83        ⁢    and  
(f) a Vsat calculation part calculating a saturation velocity given by a function of the velocity saturation coefficient U1 calculated in the U1 calculation part (b-1) and the parameter decided in the F calculation part (e) as a parameter expressing the velocity saturation effect and outputting a signal expressing the value thereof.
According to the sixth aspect, the saturation velocity is extracted as the parameter expressing the velocity saturation effect on the basis of the parameters expressing the velocity saturation coefficient and the mobility, whereby the parameter expressing the velocity saturation effect is precisely provided in a form matching with channel shortening, external resistance and channel narrowing.
The present invention is also directed to a characteristic extraction device. A characteristic extraction device according to a seventh aspect of the present invention, extracting a parameter expressing mobility of a MOS transistor, comprises (a) an f extraction part receiving signals expressing measured data of characteristics of at least two MOS transistors different only in channel length from each other and extracting channel resistance f(Vgt) per unit effective channel length as a function of a gate overdrive Vgt on the basis of the signals, (b) a DW extraction part receiving signals expressing measured data of characteristics of at least two MOS transistors different only in channel width from each other and extracting channel narrowing DW(Vgt) as a function of the gate overdrive Vgt on the basis of the signals, and (c) a xcexc calculation part deciding the parameter to fit mobility xcexc(Vgt) as a function of the gate overdrive Vgt expressed by the following relations with a capacitance Cox of a gate insulator film, a drain-to-source voltage Vds and a channel width Wm and outputting a signal expressing the value thereof:             1              μ        ⁡                  (          Vgt          )                      =                  h        ⁡                  (          Vgt          )                    ·      Cox      ·              (                  Vgt          -                      Vds            2                          )              and            h      ⁡              (        Vgt        )              =                  f        ⁡                  (          Vgt          )                    ·              (                  Wm          -                      DW            ⁢                          (              Vgt              )                                      )            
According to the seventh aspect, the parameter expressing the mobility, which is decided on the basis of the channel resistance (hereinafter referred to as xe2x80x9cparameter fxe2x80x9d) per unit effective channel length and channel narrowing, is precisely provided in a form matching with channel shortening, external resistance and channel narrowing.
According to an eighth aspect of the present invention, the f extraction part (a) includes (a-1) a device part obtaining data related to drain-to-source current Ids vs. gate-to-source voltage Vgs as to each of at least two MOS transistors different only in the channel length from each other, (a-2) a device part expressing a set of total resistance defined as Vds/Ids and the channel length for each of at least two MOS transistors different only in the channel length from each other and each of at least two gate overdrives Vgt as a data point on a graph, (a-3) a device part individually expressing each group of the data points having the gate overdrive Vgt in common in a straight line, and (a-4) a device part calculating channel resistance f(Vgt) per the, unit effective channel length as a function of the gate overdrives Vgt from slopes of the straight lines corresponding to at least two gate overdrives Vgt respectively.
According to the eighth aspect, the parameter f, which is calculated from slope of the straight lines expressing total resistance vs. channel length with different gate overdrives on the graph, is readily and precisely provided.
According to a ninth aspect of the present invention, the DW extraction part (b) includes (b-1) a device part obtaining data related to drain-to-source current Ids vs. gate-to-source voltage Vgs as to each of at least two MOS transistors different only in the channel width from each other, (b-2) a device part expressing a set of conductance defined as Ids/Vds or the drain-to-source current Ids itself and the channel width for each of at least two MOS transistors different only in the channel width from each other and each of at least two gate overdrives Vgt as a data point on a graph, (b-3) a device part individually expressing each group of the data points having the gate overdrives Vgt in common in a straight line, and (b-4) a device part calculating the channel narrowing DW(Vgt) as a function of the gate overdrives Vgt from intercepts of a coordinate axis, expressing the channel width, of the straight lines corresponding to at least two gate overdrives Vts respectively.
According to the ninth aspect, channel narrowing, which is calculated from the intercepts on the straight lines expressing the relation between the conductance (or drain-to-source current) and the channel width on the graph, is readily and precisely provided.
The present invention is also directed to a characteristic evaluation device, A characteristic evaluation device according to a tenth aspect of the present invention, evaluating characteristics of a circuit having a MOS transistor, includes (1) an E-T data extraction part, extracting E-T data of the MOS transistor, including (1-1) the characteristic extraction device according to any of the first to sixth aspects of the present invention and (1-2) the characteristic extraction device according to any of the seventh to ninth aspects of the present invention, (2) a principal component analysis part extracting independent variables by executing principal component analysis on the E-T data extracted in the E-T data extraction part (1), (3) a Monte Carlo calculation part supplying statistical dispersion to the E-T data by supplying statistical dispersion to at least part of the independent variables, and (4) a circuit simulator receiving a signal expressing the statistically dispersed E-T data obtained in the Monte Carlo calculation part (3) and a signal expressing circuit connection information which is information related to connection conditions between elements forming the circuit and executing circuit simulation related to the circuit.
According to the tenth aspect, circuit simulation is performed in consideration of statistical dispersion with mutually matching E-T data, whereby the characteristics of the circuit can be evaluated in high precision.
The present invention is also directed to a semiconductor device. A semiconductor device according to an eleventh aspect of the present invention is manufactured through the characteristic extraction device according to any of the first to ninth aspects of the present invention or the characteristic evaluation device according to the tenth aspect of the present invention.
The semiconductor device according to the eleventh aspect, which is manufactured through the device according to any of the first to ninth aspects, can be efficiently completed to a product having guaranteed characteristics.
A semiconductor device according to a twelfth aspect of the present invention comprises an integrated circuit, including a MOS transistor, formed on a semiconductor substrate, and at least three MOS transistors, formed on the semiconductor substrate, separated from the integrated circuit, while at least three MOS transistors include a set of MOS transistors different only in channel length as mask length from each other and a set of MOS transistors different only in channel width as mask width from each other while allowing overlapping, conditions provided by the following relations:             Lm      L0         greater than                   "LeftBracketingBar"                  Δ          ⁢                      xe2x80x83                    ⁢          L                "RightBracketingBar"            r                  Lm      L0         greater than                             1          r                ·                              "LeftBracketingBar"                          Δ              ⁢                              xe2x80x83                            ⁢              Rds                        "RightBracketingBar"                    Rdsi                    ⁢      Lmi                  Wm      L0         greater than                   "LeftBracketingBar"                  Δ          ⁢                      xe2x80x83                    ⁢          W                "RightBracketingBar"            r      
are satisfied for the set of MOS transistors different only in the channel length from each other in relation to deviation xcex94L between a first transistor having the maximum channel length and a second transistor having the minimum channel length in difference between finished length and mask length related to channel length, a mask length LmLO of the first transistor, deviation xcex94W between the first transistor and the second transistor in channel width as finished width, a channel width WmLO as a mask width of the first transistor, external resistance Rdsi of the second transistor, deviation xcex94Rds between the first transistor and the second transistor in external resistance, a channel length Lmi as a mask length of the second transistor, and an allowable value r for an extraction error of channel shortening relative to an effective gate length, and conditions provided by the following relations:             Lm      W1         greater than                   "LeftBracketingBar"                  Δ          ⁢                      xe2x80x83                    ⁢          L                "RightBracketingBar"            r                  Wm      W1         greater than                   "LeftBracketingBar"                  Δ          ⁢                      xe2x80x83                    ⁢          W                "RightBracketingBar"            r      
are satisfied for the set of MOS transistors different only in the channel width from each other in relation to deviation xcex94W between a first transistor having the maximum channel width and a second transistor having the minimum channel width in difference between finished width and mask width related to channel width, a mask width WmWI of the first transistor, deviation xcex94L between the first transistor and the second transistor in channel width as finished width, a channel length LmWI as a mask length of the first transistor, and an allowable value r for an extraction error of channel narrowing relative to an effective gate width.
According to the twelfth aspect, at least three MOS transistors satisfying prescribed conditions related to channel dimensions are formed on the same semiconductor substrate independently of the integrated circuit, whereby E-T data related to MOS transistors forming the integrated circuit can be extracted with prescribed precision.
The present invention is also directed to a characteristic extraction method. A characteristic extraction method according to a thirteenth aspect of the present invention, extracting a parameter expressing a velocity saturation effect of a MOS transistor, comprises steps of (a) extracting an effective channel length for at least two drain-to-source voltages, and (b) calculating the parameter on the basis of the extracted effective channel length.
According to the thirteenth aspect, since the parameter expressing the velocity saturation effect is extracted on the basis of the effective channel length, the parameter is precisely extracted in a form matching with channel shortening and external resistance, which are other parameters forming the E-T data.
According to a fourteenth aspect of the present invention, the step (b) includes a step (b-1) of regarding the effective channel length as a function Le(Vds) of the drain-to-source voltages Vds and assuming the following relation with another parameter Leff:
Le(Vds)=Leff+U1xc2x7Vds
thereby calculating a velocity saturation coefficient U1 as the parameter expressing the velocity saturation effect.
According to the fourteenth aspect, the velocity saturation coefficient is precisely extracted as the parameter expressing the velocity saturation effect in a form matching with channel shortening and external resistance.
According to a fifteenth aspect of the present invention, the at least two drain-to-source voltages are two drain-to-source voltages Vds1 abd Vds2, and the step (b-1) includes steps of (b-1-1) expressing a set of values Le(Vds1) and Le(Vds2) of the function calculated by using the relation for the two drain-to-source voltages Vds1 and Vds2 as a data point on a graph for each of at least two MOS transistors, (b-1-2) expressing a group of the data points in a straight line on the graph, and (b-1-3) obtaining the velocity saturation coefficient U1 by dividing the value Le(Vds2) at the Le(Vds1) being about zero on the straight line by the difference Vds2xe2x88x92Vds1 between Vds1 and Vds2.
According to the fifteenth aspect, the velocity saturation coefficient, which is obtained on the basis of an intercept on a straight line expressing a set of values Leff (Vds1) and Leff(Vds2) of the function on a graph or an approximate value thereof, is readily and precisely provided.
According to a sixteenth aspect of the present invention, the at least two drain-to-source voltages are two drain-to-source voltages Vds1 and Vds2, and the step (b-1) includes steps of (b-1-1) expressing a set of a ratio Le(Vds2)/Le(Vds1) and an inverse 1/Le(Vds1) obtained from values Le(Vds1) and Le(Vds2) of the function calculated by using the relation for the two drain-to-source voltages Vds1 and Vds2 as data a point on a graph for each of at least two MOS transistors, (b-1-2) expressing a group of the data points in a straight line on the graph, and (b-1-3) obtaining the velocity saturation coefficient U1 by dividing slope of the straight line by the difference Vds2xe2x88x92Vds1 between the value Vds1 and the value Vds2.
According to the sixteenth aspect, the velocity saturation coefficient, which is obtained on the basis of slope of the straight line expressing the set of Leff(Vds1)/Leff(Vds2) and 1/Leff(Vds1) on the graph, is readily and precisely provided.
According to a seventeenth aspect of the present invention, the step (a) includes steps of (a-1) receiving data related to drain-to-source currents Ids vs. gate-to-source voltages Vgs under at least two drain-to-source voltages Vds as to at least two MOS transistors different only in channel length from each other, (a-2) expressing a set of total resistance defined as Vds/Ids and the channel length for each of at least two MOS transistors, each of at least two drain-to-source voltages Vds and each of at least two gate overdrives Vgt as data points on a graph, (a-3) individually expressing each group of the data points having both of the drain-to-source voltage Vds and the gate overdrive Vgt in common in a straight line, and (a-4) calculating the effective channel length for each of at least two drain-to-source voltages Vds from an intersection between the straight lines having the different gate overdrives Vts.
According to the seventeenth aspect, the effective channel length, which is calculated from the intersection of the straight lines expressing total resistance vs. channel length with different gate overdrives on the graph, is readily and precisely provided.
The present invention is also directed to a characteristic extraction method. A characteristic extraction method according to an eighteenth aspect of the present invention, extracting a parameter expressing mobility of a MOS transistor, comprises steps of (a) extracting channel resistance f(Vgt) per unit effective channel length as a function of a gate overdrive Vgt from at least two MOS transistors different only in channel length from each other, (b) extracting channel narrowing DW(Vgt) as a function of the gate overdrive Vgt from at least two MOS transistors different only in channel width from each other, and (c) deciding the parameter to fit mobility xcexc(Vgt) as a function of the gate overdrive Vgt expressed by the following relations with a capacitance Cox of a gate insulator film, a drain-to-source voltage Vgs and a channel width Wm:             1              μ        ⁡                  (          Vgt          )                      =                  h        ⁡                  (          Vgt          )                    ·      Cox      ·              (                  Vgt          -                      Vds            2                          )              and            h      ⁡              (        Vgt        )              =                  f        ⁡                  (          Vgt          )                    ·                        (                      Wm            -                          DW              ⁡                              (                Vgt                )                                              )                .            
According to the eighteenth aspect, the parameter expressing the mobility, which is decided on the basis of the channel resistance (hereinafter referred to as xe2x80x9cparameter fxe2x80x9d) per unit effective length and channel narrowing, is precisely provided in a form matching with channel shortening, external resistance and channel narrowing.
According to a nineteenth aspect of the present invention, the step (a) includes steps of (a-1) obtaining data related to drain-to-source current Ids vs. gate-to-source voltage Vgs as to each of at least two MOS transistors different only in channel length from each other, (a-2) expressing a set of total resistance defined as Vds/Ids and the channel length for each of at least two MOS transistors different only in the channel length from each other and each of at least two gate overdrives Vgt as a data point on a graph, (a-3) individually expressing each group of the data points having the gate overdrive Vgt in common in a straight line, and (a-4) calculating channel resistance f(Vgt) per the unit effective channel length as a function of the gate overdrives Vgt from slope of the straight lines corresponding to at least two gate overdrives Vgs respectively.
According to the nineteenth aspect, the parameter f, which is calculated from slope of the straight lines expressing the total resistance vs. channel lengths with different gate overdrives on the graph, is readily and precisely provided.
According to a twentieth aspect of the present invention, the step (b) includes steps of (b-1) obtaining data related to drain-to-source current Ids vs. gate-to-source voltage Vgs as to each of the at least two MOS transistors different only in channel width from each other, (b-2) expressing a set of conductance defined as Ids/Vds or drain-to-source current Ids itself and the channel width for each of at least two MOS transistors different only in the channel width from each other and each of at least two gate overdrives Vgt as a data point on a graph, (b-3) individually expressing each group of the data points having the gate overdrive Vgt in common in a straight line, and (b-4) calculating the channel narrowing DW(Vgt) as a function of the gate overdrive Vgt from intercepts of a coordinate axis, expressing the channel width, of the straight lines corresponding to at least two gate overdrives Vts respectively.
According to the twentieth aspect, channel narrowing, which is calculated from the intercepts on the straight lines expressing the relation between the conductance (or drain-to-source current) and the channel widths on the graph, is readily and precisely provided.
A characteristic extraction method according to a twenty-first aspect of the present invention, extracting a parameter expressing a velocity saturation effect of a MOS transistor, comprises steps of (A) extracting the velocity saturation coefficient U1 with the characteristic extraction method according to any of the fourteenth to sixteenth aspects of the present invention, (B) extracting the parameter expressing the mobility with the characteristic extraction method according to any of the eighteenth to twentieth aspects of the present invention, and (C) calculating a saturation velocity given by a function of the velocity saturation coefficient U1 extracted in the step (A) and the parameter extracted in the step (B) as the parameter expressing the velocity saturation effect.
According to the twenty-first aspect, the saturation velocity, extracted as the parameter expressing the velocity saturation effect on the basis of the parameters expressing the velocity saturation coefficient and the mobility, is precisely provided in a form matching with channel shortening, external resistance and channel narrowing.
According to a twenty-second aspect of the present invention, at least two MOS transistors different only in the channel length from each other are at least two MOS transistors different only in channel length as mask length from each other, and conditions provided by the following relations:             Lm      L0         greater than                   "LeftBracketingBar"                  Δ          ⁢                      xe2x80x83                    ⁢          L                "RightBracketingBar"            r                  Lm      L0         greater than                             1          r                ·                              "LeftBracketingBar"                          Δ              ⁢                              xe2x80x83                            ⁢              Rds                        "RightBracketingBar"                    Rdsi                    ⁢      Lmi                  Wm      L0         greater than                   "LeftBracketingBar"                  Δ          ⁢                      xe2x80x83                    ⁢          W                "RightBracketingBar"            r      
are satisfied in relation to deviation AL between a first transistor having the maximum channel length and a second transistor having the minimum channel length in difference between finished length and mask length related to channel length, a mask length LmLO of the first transistor, deviation xcex94W between the first transistor and the second transistor in channel width as finished width, a channel width WmLO as a mask width of the first transistor, external resistance Rdsi of the second transistor, deviation xcex94Rds between the first transistor and the second transistor in external resistance, a channel length Lmi as a mask length of the second transistor, and an allowable value r for an extraction error of channel shortening relative to an effective gate length.
According to the twenty-second aspect, conditions related to channel sizes are provided as to the MOS transistors subjected to extraction of E-T data, whereby extraction can be performed within a prescribed range of extraction errors.
According to a twenty-third aspect of the present invention, at least two MOS transistors different only in the channel width from each other are at least two MOS transistors different only in channel width as mask width from each other, and conditions provided by the following relations:             Lm      W1         greater than                   "LeftBracketingBar"                  Δ          ⁢                      xe2x80x83                    ⁢          L                "RightBracketingBar"            r                  Wm      W1         greater than                   "LeftBracketingBar"                  Δ          ⁢                      xe2x80x83                    ⁢          W                "RightBracketingBar"            r      
are satisfied in relation to deviation xcex94W between a first transistor having the maximum channel width and a second transistor having the minimum channel width in difference between finished width and mask width related to channel width, a mask width WmWI of the first transistor, deviation xcex94L between the first transistor and the second transistor in channel length as finished length, a channel length LmWI as a mask length of the first transistor, and an allowable value r for an extraction error of channel narrowing relative to an effective gate width.
According to the twenty-third aspect, conditions related to channel sizes are provided as to the MOS transistors subjected to extraction of E-T data, whereby extraction can be performed within a prescribed range of extraction errors.
The present invention is also directed to a characteristic evaluation method. A characteristic evaluation method according to a twenty-fourth aspect of the present invention, evaluating characteristics of a circuit having a MOS transistor, comprises steps of (1) extracting E-T data of the MOS transistor, including steps of (1-1) extracting the parameter expressing the velocity saturation effect of the MOS transistor with the characteristic extraction method according to any of the thirteenth to seventeenth aspects of the present invention, and (1-2) extracting the parameter expressing the mobility of the MOS transistor with the characteristic extraction method according to any of the eighteenth to twentieth aspects of the present invention, (2) extracting independent variables by executing principal component analysis on the E-T data extracted in the step (1), (3) supplying statistical dispersion to the E-T data by supplying statistical dispersion to at least part of the independent variables, and (4) executing circuit simulation with the statistically dispersed E-T data obtained in the step (3) and circuit connection information which is information related to connection conditions between elements forming the circuit.
According to the twenty-fourth aspect, circuit simulation is performed in consideration of statistic dispersion with mutually matching E-T data, whereby the characteristics of the circuit can be evaluated in high precision.
The present invention is also directed to a recording medium. A recording medium according to a twenty-fifth aspect of the present invention records a program, 15 readable by a computer, defining an operation of the computer, and the recording medium records a program, as the program, defining the characteristic extraction method according to any of the thirteenth to twenty-third aspects of the present invention or the characteristic evaluation method according to the twenty-fourth aspect of the present invention.
According to the twenty-fifth aspect, the recording medium records the program defining the method according to any of the thirteenth to twenty-fourth aspects, whereby the method according to any of the thirteenth to twenty-fourth aspects can be carried out by connecting the recording medium to the computer.
The present invention has been proposed in order to solve the aforementioned problems of the prior art, and an object thereof is to obtain a characteristic extraction technique and a characteristic evaluation technique extracting E-T data of a MOSFET in a mutually matching form thereby enabling highly precise characteristic evaluation, and to provide a semiconductor device manufactured through these techniques, a recording medium suitable for these techniques, and a semiconductor device enabling precise extraction of E-T data through the characteristic extraction technique and the characteristic evaluation technique.